Integrated circuit (IC) fabrication processes include, among other things, lithographic processes that transfer predetermined IC layout patterns provided on the masks to various layers of materials for forming different elements on a wafer. In some applications, the predetermined IC layout patterns on a mask are first transferred to a photoresist layer and optionally to a patterned hard mask layer according to the patterned photoresist layer. Based on the patterned photoresist layer and/or the patterned hard mask layer, one or more etching or deposition processes are performed to form the elements as defined by the mask. Prior to the next pattern transferring stage, a wafer inspection process is sometimes performed to identify defect candidates for the wafer. The defect candidates may include actual defects and false alarms (i.e., false defects). The defect candidates are further examined using a Scanning Electron Microscope (SEM), and one or more remedial measures are taken according to a result of the SEM examination.